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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the MAX1403 18-bit, low-power, multichannel, serial- output analog-to-digital converter (adc) features matched 200? current sources for sensor excitation. this adc uses a sigma-delta modulator with a digital decimation filter to achieve 16-bit accuracy. the digital filter? user-selectable decimation factor allows the con- version resolution to be reduced in exchange for a higher output data rate. true 16-bit performance is achieved at an output data rate of up to 480sps. in addition, the modulator sampling frequency may be optimized for either lowest power dissipation or highest throughput rate. the MAX1403 operates from +3v. this device offers three fully differential input channels that may be independently programmed with a gain between +1v/v and +128v/v. furthermore, it can com- pensate an input-referred dc offset up to 117% of the selected full-scale range. these three differential chan- nels may also be configured to operate as five pseudo- differential input channels. two additional, fully differential system-calibration channels are provided for gain and offset error correction. the MAX1403 can be configured to sequentially scan all signal inputs and provide the results via the serial inter- face with minimum communications overhead. when used with a 2.4576mhz or 1.024mhz master clock, the digital decimation filter can be programmed to produce zeros in its frequency response at the line frequency and associated harmonics, ensuring excellent line rejection without the need for further postfiltering. the MAX1403 is available in a 28-pin ssop package. applications portable industrial instruments portable weigh scales loop-powered systems pressure transducers features ? 18-bit resolution, sigma-delta adc ? 16-bit accuracy with no missing codes to 480sps ? matched on-board current sources (200?) for sensor excitation ? low quiescent current 250? (operating mode) 2? (power-down mode) ? 3 fully differential or 5 pseudo-differential signal input channels ? 2 additional, fully differential calibration channels/auxiliary input channels ? programmable gain and offset ? fully differential reference inputs ? converts continuously or on command ? automatic channel scanning and continuous data output mode ? operates with analog and digital supplies from +2.7v to +3.6v ? spi/qspi-compatible 3-wire serial interface ? 28-pin ssop package MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 sclk din dout int v dd dgnd ain5 caloff+ caloff- refin+ refin- calgain+ calgain- ain6 ain4 ain3 ain2 ain1 v+ agnd out1 out2 ds0 ds1 reset cs clkout clkin ssop top view MAX1403 part MAX1403cai MAX1403eai -40? to +85? 0? to +70? temp. range pin-package 28 ssop 28 ssop pin configuration ordering information evaluation kit available spi and qspi are trademarks of motorola, inc. 19-1481; rev 0; 4/99
fs1 = 0; mf1, mf0 = 1, MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to agnd, dgnd .................................................-0.3v to +6v v dd to agnd, dgnd ...............................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v analog inputs to agnd................................-0.3v to (v+ + 0.3v) analog outputs to agnd .............................-0.3v to (v+ + 0.3v) reference inputs to agnd...........................-0.3v to (v+ + 0.3v) clkin and clkout to dgnd...................-0.3v to (v dd + 0.3v) all other digital inputs to dgnd..............................-0.3v to +6v all digital outputs to dgnd .......................-0.3v to (v dd + 0.3v) maximum current input into any pin ..................................50ma continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.52mw/? above +70?) ........524mw operating temperature ranges MAX1403cai .....................................................0? to +70? MAX1403eai...................................................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10sec) .............................+300? ?/? for gains of 1, 2, 4 no missing codes guaranteed by design; for filter settings with fs1 = 0 for gains of 1, 2, 4, 8, 16, 32, 64 for gain of 128 for gains of 1, 2, 4, 8, 16, 32, 64 for gain of 128 for gains of 1, 2, 4, 8, 16, 32, 64 for gain of 128 for gains of 1, 2, 4 for gains of 1, 2, 4, 8, 16, 32, 64 for gains of 8, 16, 32, 64, 128 for gains of 1, 2, 4 depends on filter setting and selected gain relative to nominal of 1% fsr for gains of 8, 16, 32, 64, 128 conditions 0.8 %fsr -2.5 2.5 bipolar negative full-scale error ppm/? 5 gain-error drift (note 6) 1 %fsr -3 3 gain error (note 5) -2 2 %fsr -3.5 3.5 -2.5 2.5 positive full-scale error (note 3) 0.3 bipolar zero drift bits 16 noise-free resolution 0.8 %fsr -2.0 2.0 bipolar zero error ?/? 0.3 unipolar offset drift 0.5 (tables 16a, 16b) output noise %fsr -0.0015 0.0015 inl integral nonlinearity (note 1) 0.98 nominal gain (note 2) %fsr -1 2 unipolar offset error units min typ max symbol parameter for gains of 8, 16, 32, 64, 128 ?/? 0.3 bipolar negative full-scale drift for gains of 8, 16, 32, 64, 128 for gains of 1, 2, 4 ?/? 0.3 0.8 full-scale drift (note 4) for gain of 128 -3.5 3.5 ?.001 static performance fs1 = 0; mf1, mf0 = 1, 2, 3 bipolar mode; fs1 = 0; mf1, mf0 = 0
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) buff = 0 buff = 1 bipolar mode refin and ain for buff = 0 buff = 1 unipolar mode refin and ain for buff = 0 refin and ain for buff = 0 for filter notch 60hz, ?.02 f notch , mf1 = 0, mf0 = 0, f clkin = 2.4576mhz for filter notch 50hz, ?.02 f notch , mf1 = 0, mf0 = 0, f clkin = 2.4576mhz at dc for filter notch 60hz, ?.02 f notch , mf1 = 0, mf0 = 0, f clkin = 2.4576mhz (note 9) dac code = 0000 unipolar mode bipolar mode input referred for filter notch 50hz, ?.02 f notch , mf1 = 0, mf0 = 0, f clkin = 2.4576mhz (note 9) conditions pf 34 ain input capacitance (notes 12) na 10 ain input current (note 11) na 10 pa 40 dc input leakage current (note 11) v v agnd v+ + 200mv - 1.5 absolute and common-mode ain voltage range v v agnd v+ - 30mv + 30mv absolute input voltage range v v agnd v+ common-mode voltage range (note 10) db 100 nmr normal mode 60hz rejection (note 9) db 100 nmr normal mode 50hz rejection (note 9) 150 150 -58.35 58.35 %fsr -116.7 116.7 offset dac range (note 7) db 90 cmr common-mode rejection ? rms 0 additional noise from offset dac (note 8) %fsr 16.7 offset dac resolution 8.35 %fsr -2.5 2.5 offset dac full-scale error %fsr 0 offset dac zero-scale error units min typ max symbol parameter t a = +25? t a = t min to t max 38 45 60 buff = 1, all gains 30 unipolar input range (u/ b bit = 1) v 0 to v ref / gain ain differential voltage range (note 13) bipolar input range (u/ b bit = 0) ? ref / gain gain = 1 gain = 2 gain = 4 gain = 8, 16, 32, 64, 128 offset dac analog inputs/reference inputs (specifications for ain and refin, unless otherwise noted.)
+3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) MAX1403 v dd - 0.3 compliance voltage range v agnd v+ - 1.0 drift match 5 match ? out1 to out2 drift 100 initial tolerance 15 current i exc 200 v dd - 0.3 dout and int, i source = 100? output high voltage (note 15) v oh 0.4 clkout, i sink = 10? drift ?.05 initial tolerance ?0 current i bo 0.1 input high voltage v ih v mv v v v ppm/? % ppm/? % ua %/? % ? pf ? clkin only all inputs except clkin 2.4 2 refin+ - refin- voltage (note 14) 1.25 v ? v ?% for specified performance; functional with lower v ref input low voltage v il 0.4 floating-state leakage current i l -10 10 floating-state output capacitance c o dout and int, i sink = 100? 9 output low voltage (note 15) v ol input hysteresis v hys all inputs except clkin clkin only 200 input current i in -10 +10 all inputs except clkin 0.4 0.4 parameter symbol min typ max units ain and refin input sampling frequency f s (table 15) hz conditions clkout, i source = 10? transducer excitation currents transducer burn-out (note 16) logic inputs logic outputs power-supply rejection v+ (note 17) psr (note 18) v dd voltage v dd 2.7 3.6 v+ voltage v+ 2.7 3.6 for specified performance db v v power requirements
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc _______________________________________________________________________________________ 5 2.4576mhz 1.024mhz buffers off buffers off buffers on 2.4576mhz 1.024mhz 370 420 buffers off buffers off buffers on normal mode, mf1 = 0, mf0 = 0 610 700 250 300 buffers on 610 buffers on 2x mode, mf1 = 0, mf0 = 1 1.2 1.5 conditions pd bit = 1, external clock stopped 0.42 0.55 245 2.4576mhz 1.024mhz buffers off buffers off buffers on 2.4576mhz 1.024mhz 1.2 buffers off buffers off buffers on 4x mode, mf1 = 1, mf0 = 0 ? 4.8 6 110 1.8 2.2 buffers on 4.8 buffers on 8x mode, mf1 = 1, mf0 = 1 ma 4.8 6 i v+ v+ current 1.8 2.2 1.8 0.42 v+ standby current (note 19) 0.08 70 200 2x mode, mf1 = 0, mf0 = 1 0.17 0.35 normal mode, mf1 = 0, mf0 = 0 pd bit = 1, external clock stopped 110 150 300 ? v dd standby current (note 19) ? 1.024mhz 2.4576mhz 1.024mhz 175 210 2.4576mhz 0.15 0.11 8x mode, mf1 = 1, mf0 = 1 0.32 0.50 ma 4x mode, mf1 = 1, mf0 = 0 0.22 0.40 1.024mhz 2.4576mhz i dd digital supply current 1.024mhz 2.4576mhz units min typ max symbol parameter ? electrical characteristics (continued) (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) analog power-supply current (measured with digital inputs at either dgnd or v dd , external clkin, burn-out and transducer excitation currents disabled, x2clk = 0, clk = 0 for 1.024mhz, clk = 1 for 2.4576mhz.) digital power-supply current (measured with digital inputs at either dgnd or v dd , external clkin, burn-out and transducer excitation currents disabled, x2clk = 0, clk = 0 for 1.024mhz, clk = 1 for 2.4576mhz.)
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 6 _______________________________________________________________________________________ note 1: contact factory for inl limits applicable with fs1 = 0 and mf1, mf0 = 1, 2, or 3. note 2: nominal gain is 0.98. this ensures a full-scale input voltage may be applied to the part under all conditions without caus- ing saturation of the digital output data. note 3: positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. this error does not include the nominal gain of 0.98. note 4: full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipol ar input ranges. note 5: gain error does not include zero-scale errors. it is calculated as (full-scale error - unipolar offset error) for unipolar rang es and as (full-scale error - bipolar zero error) for bipolar ranges. this error does not include the nominal gain of 0.98. note 6: gain-error drift does not include unipolar offset drift or bipolar zero drift. it is effectively the drift of the part if zero- scale error is removed. note 7: use of the offset dac does not imply that any input may be taken below agnd. note 8: additional noise added by the offset dac is dependent on the filter cutoff, gain, and dac setting. no noise is added for a dac code of 0000. note 9: guaranteed by design or characterization; not production tested. note 10: the absolute input voltage must be within the input voltage range specification. note 11: all ain and refin pins have identical input structures. leakage is production tested only for the ain3, ain4, ain5, calgain, and caloff inputs. note 12: the dynamic load presented by the MAX1403 analog inputs for each gain setting is discussed in detail in the switching network section . values are provided for the maximum allowable external series resistance. note 13: the input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen- tial or pseudo-differential pair. table 5 shows which inputs form differential pairs. note 14: v ref = v refin+ - v refin- . note 15: these specifications apply to clkout only when driving a single cmos load. 2.4576mhz 1.024mhz buffers off buffers off buffers on 2.4576mhz 1.024mhz 1.45 2.05 buffers off buffers off buffers on normal mode, mf1 = 0, mf0 = 0 2.51 3.30 1.32 1.98 buffers on 2.28 buffers on 2x mode, mf1 = 0, mf0 = 1 4.53 6.11 conditions 1.95 2.97 1.08 2.4576mhz 1.024mhz buffers off buffers off buffers on 2.4576mhz 1.024mhz 4.32 buffers off buffers off buffers on 4x mode, mf1 = 1, mf0 = 0 16.6 21.2 6.67 8.58 buffers on 16.4 buffers on 8x mode, mf1 = 1, mf0 = 1 mw 16.9 21.45 pd power dissipation 7.0 8.91 6.44 1.75 (note 19) 770 ? standby power dissipation 0.81 1.36 units min typ max symbol parameter electrical characteristics (continued) (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) power dissipation (v+ = v dd = +3.3v, digital inputs = 0 or v dd , external clkin, burn-out and transducer excitation currents disabled, x2clk = 0, clk = 0 for 1.024mhz, clk = 1 for 2.4576mhz.)
0 100 MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc _______________________________________________________________________________________ 7 timing characteristics (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, agnd = dgnd, f clkin = 2.4576mhz, input logic 0 = 0v, logic 1 = v dd , t a = t min to t max , unless otherwise noted.) (notes 20, 21, 22) bus relinquish time after sclk rising edge (note 27) t 10 ns sclk falling edge to data valid delay (notes 25, 26) t 6 0 100 ns int high time t int 560 / n t clkin ns x2clk = 1, n = 2 (2 ? mf1 + mf0) crystal oscillator or clock exter- nally supplied for specified perfor- mance (notes 23, 24) sclk setup to falling edge cs t 4 30 ns sclk low pulse width t 8 100 ns 10 100 sclk rising edge to int high (note 28) t 11 200 cs rising edge to sclk rising edge hold time (note 22) t 9 0 ns sclk high pulse width t 7 100 ns cs falling edge to sclk falling edge setup time t 5 30 ns 280 / n ? t clkin int to cs setup time (note 9) t 3 x2clk = 0, n = 2 (2 ? mf1 + mf0) 0 ns reset pulse width low t 2 100 ns master clock input low time f clkin lo 0.4 t clkin ns t clkin = 1 / f clkin , x2clk = 0 master clock input high time f clkin hi 0.4 t clkin ns t clkin = 1 / f clkin , x2clk = 0 master clock frequency f clkin 0.8 5.0 mhz parameter symbol min typ max units 0.4 2.5 conditions ns x2clk = 0 x2clk = 1 note 16: the burn-out currents require a 500mv overhead between the analog input voltage and both v+ and agnd to operate correctly. note 17: measured at dc in the selected passband. psr at 50hz will exceed 120db with filter notches of 25hz or 50hz and fast bit = 0. psr at 60hz will exceed 120db with filter notches of 20hz or 60hz and fast bit = 0. note 18: psr depends on gain. for a gain of +1v/v, psr is 70db typical. for a gain of +2v/v, psr is 75db typical. for a gain of +4v/v, psr is 80db typical. for gains of +8v/v to +128v/v, psr is 85db typical. note 19: standby power-dissipation and current specifications are valid only with clkin driven by an external clock and with the external clock stopped. if the clock continues to run in standby mode, the power dissipation will be considerably higher. when used with a resonator or crystal between clkin and clkout, the actual power dissipation and i dd in standby mode will depend on the resonator or crystal type. 30 ns t 12 sclk setup to falling edge cs serial-interface read operation serial-interface write operation
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 8 _______________________________________________________________________________________ note 20: all input signals are specified with t r = t f = 5ns (10% to 90% of v dd ) and timed from a voltage level of 1.6v. note 21: see figure 4. note 22: timings shown in tables are for the case where sclk idles high between accesses. the part may also be used with sclk idling low between accesses, provided cs is toggled. in this case sclk in the timing diagrams should be inverted and the terms ?clk falling edge?and ?clk rising edge?exchanged in the specification tables. if cs is permanently tied low, the part should only be operated with sclk idling high between accesses. note 23: clkin duty cycle range is 45% to 55%. clkin must be supplied whenever the MAX1403 is not in standby mode. if no clock is present, the device can draw higher current than specified. note 24: the MAX1403 is production tested with f clkin at 2.5mhz (1mhz for some i dd tests). note 25: measured with the load circuit of figure 1 and defined as the time required for the output to cross the v ol or v oh limits. note 26: for read operations, sclk active edge is falling edge of sclk. note 27: derived from the time taken by the data output to change 0.5v when loaded with the circuit of figure 1. the number is then extrapolated back to remove effects of charging or discharging the 50pf capacitor. this ensures that the times quot- ed in the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances. note 28: int returns high after the first read after an output update. the same data can be read again while int is high, but be careful not to allow subsequent reads to occur close to the next output update. note 29: auxiliary inputs ds0 and ds1 are latched on the first falling edge of sclk during a data-read cycle. sclk high pulse width t 16 100 ns sclk low pulse width t 17 100 ns data valid to sclk rising edge hold time t 15 0 ns parameter symbol min typ max units cs falling edge to sclk falling edge setup time t 13 30 ns data valid to sclk rising edge setup time t 14 30 ns conditions timing characteristics (continued) (v+ = +2.7v to +3.6v, v dd = +2.7v to +3.6v, agnd = dgnd, f clkin = 2.4576mhz, input logic 0 = 0v, logic 1 = v dd , t a = t min to t max , unless otherwise noted.) (notes 20, 21, 22) cs rising edge to sclk rising edge hold time t 18 0 ns ds0/ds1 to sclk falling edge hold time (notes 21, 29) t 20 0 ns ds0/ds1 to sclk falling edge setup time (notes 21, 29) t 19 40 ns 100 m a at v dd = +3.3v to output pin 50pf 100 m a at v dd = +3.3v figure 1. load circuit for bus-relinquish time and v ol and v oh levels auxiliary digital inputs (ds0 and ds1)
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc _______________________________________________________________________________________ 9 0 50 100 150 200 250 0 1.0 0.5 1.5 2.0 2.5 3.0 3.5 out1 and out2 compliance max1402 toc01 compliance voltage (v) output current ( m a) v+ = +3.3v -15 0 -5 -10 5 10 15 differential nonlinearity MAX1403-02 differential input voltage (v) dnl (ppm) -1.0 -0.5 0 0.5 1.0 480sps gain = +1v/v 262, 144 pts -15 0 -5 -10 5 10 15 -1.0 -0.5 0 0.5 1.0 MAX1403-03 differential input voltage (v) inl (ppm) integral nonlinearity 480sps gain = +1v/v 262, 144 pts 0 100 50 200 150 300 250 350 -50 0 25 -25 50 75 100 v dd supply current vs. temperature (20sps output data rate unbuffered) MAX1403 toc04 temperature ( c) v dd supply current ( m a) v dd = +3.6v (note 30) 0 100 50 200 150 300 250 350 400 -50 0 25 -25 50 75 100 v+ supply current vs. temperature (20sps output data rate) MAX1403 toc07 temperature ( c) v+ supply current ( m a) buffered unbuffered 0 100 50 200 150 300 250 350 -50 0 25 -25 50 75 100 v dd supply current vs. temperature (60sps output data rate unbuffered) MAX1403 toc05 temperature ( c) v dd supply current ( m a) v dd = +3.6v (note 30) 0 100 50 200 150 300 250 350 -50 0 25 -25 50 75 100 v dd supply current vs. temperature (120sps output data rate unbuffered) MAX1403 toc06 temperature ( c) v dd supply current ( m a) v dd = +3.6v (note 30) 0 200 100 400 300 600 500 -50 0 25 -25 50 75 100 v+ supply current vs. temperature (60sps output data rate) MAX1403 toc08 temperature ( c) v+ supply current ( m a) buffered unbuffered 0 400 200 800 600 1200 1000 -50 0 25 -25 50 75 100 v+ supply current vs. temperature (120sps output data rate) MAX1403 toc09 temperature ( c) v+ supply current ( m a) buffered unbuffered typical operating characteristics (v+ = +3v, v dd = +3v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, transducer excitation currents disabled, t a = +25?, unless otherwise noted.)
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 10 ______________________________________________________________________________________ 0 100 50 250 200 150 400 350 300 450 -50 0 -25 25 50 75 100 v dd supply current vs. temperature (240sps output data rate unbuffered) MAX1403 toc10 temperature (?) v dd supply current ( m a) v dd = +3.6v (note 30) 0 200 100 400 300 600 500 -50 0 25 -25 50 75 100 v dd supply current vs. temperature (480sps output data rate unbuffered) MAX1403 toc11 temperature (?) v dd supply current ( m a) v dd = +3.6v (note 30) 0 2000 1000 4000 3000 5000 -50 0 25 -25 50 75 100 v+ supply current vs. temperature (240sps output data rate) MAX1403 toc12 temperature ( c) v+ supply current ( m a) buffered unbuffered 0 2000 1000 4000 3000 5000 -50 0 25 -25 50 75 100 v+ supply current vs. temperature (480sps output data rate) MAX1403 toc13 temperature ( c) v+ supply current ( m a) buffered unbuffered typical operating characteristics (continued) (v+ = +3v, v dd = +3v, v refin+ = +1.25v, refin- = agnd, f clkin = 2.4576mhz, transducer excitation currents disabled, t a = +25?, unless otherwise noted.) note 30: minimize capacitive loading at clkout for lowest v dd supply current. typical operating characteristics show v dd supply current with clkout loaded by 120pf.
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 11 pin description 15 ain5 analog input channel 5. used as a differential or pseudo-differential input with ain6 (see on-chip registers section). name function 1 clkin clock input. a crystal can be connected across clkin and clkout. alternatively, drive clkin with a cmos-compatible clock at a nominal frequency of 2.4576mhz or 1.024mhz, and leave clkout uncon- nected. frequencies of 4.9152mhz and 2.048mhz may be used if the x2clk control bit is set to 1. pin 2 clkout clock output. when deriving the master clock from a crystal, connect the crystal between clkin and clkout. in this mode, the on-chip clock signal is not available at clkout. leave clkout unconnected when clkin is driven with an external clock. 3 cs chip-select input. this active-low logic input is used to enable the digital interface. with cs hard-wired low, the MAX1403 operates in its 3-wire interface mode with sclk, din, and dout used to interface to the device. cs is used either to select the device in systems with more than one device on the serial bus, or as a frame-synchronization signal for the MAX1403, when a continuous sclk is used. 4 reset active-low reset input. drive low to reset the control logic, interface logic, digital filter, and analog modu- lator to power-on status. reset must be high and clkin must be toggling in order to exit reset. 5 ds1 digital input for auxiliary data input bit 1. the status of this bit is reflected in the output data by bit d4. used to communicate the status of ds1 via the serial interface. 6 ds0 digital input for auxiliary data input bit 0. the status of this bit is reflected in the output data by bit d3. used to communicate the status of ds0 via the serial interface. 7 out2 transducer excitation current source 2 8 out1 transducer excitation current source 1 9 agnd analog ground. reference point for the analog circuitry. agnd connects to the ic substrate. 10 v+ analog positive supply voltage (+2.7v to +3.6v). 11 ain1 analog input channel 1. may be used as a pseudo-differential input with ain6 as common, or as the posi- tive input of the ain1/ain2 differential analog input pair (see on-chip registers section). 12 ain2 analog input channel 2. may be used as a pseudo-differential input with ain6 as common, or as the neg- ative input of the ain1/ain2 differential analog input pair (see on-chip registers section). 13 ain3 analog input channel 3. may be used as a pseudo-differential input with ain6 as common, or as the posi- tive input of the ain3/ain4 differential analog input pair (see on-chip registers section). 14 ain4 analog input channel 4. may be used as a pseudo-differential input with ain6 as common, or as the neg- ative input of the ain3/ain4 differential analog input pair (see on-chip registers section). 16 ain6 analog input 6. may be used as a common point for ain1 through ain5 in pseudo-differential mode, or as the negative input of the ain5/ain6 differential analog input pair (see on-chip registers section). 17 calgain- negative gain calibration input. used for system gain calibration. it forms the negative input of a fully differential input pair with calgain+. normally these inputs are connected to reference voltages in the system. when system gain calibration is not required and the auto-sequence mode is used, the calgain+/calgain- input pair provides an additional fully differential input channel. 18 calgain+ positive gain calibration input. used for system gain calibration. it forms the positive input of a fully differential input pair with calgain-. normally these inputs are connected to reference voltages in the system. when system gain calibration is not required and the auto-sequence mode is used, the calgain+/calgain- input pair provides an additional fully differential input channel.
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 12 ______________________________________________________________________________________ pin description (continued) name function pin 19 refin- negative differential reference input. bias refin- between v+ and agnd, provided that refin+ is more positive than refin-. 20 refin+ positive differential reference input. bias refin+ between v+ and agnd, provided that refin+ is more positive than refin-. 21 caloff- negative offset calibration input. used for system offset calibration. it forms the negative input of a fully differential input pair with caloff+. normally these inputs are connected to zero-reference voltages in the system. when system offset calibration is not required and the auto-sequence mode is used, the caloff+/caloff- input pair provides an additional fully differential input channel. 22 caloff+ positive offset calibration input. used for system offset calibration. it forms the positive input of a fully differential input pair with caloff-. normally these inputs are connected to zero-reference voltages in the system. when system offset calibration is not required and the auto-sequence mode is used, the caloff+/caloff- input pair provides an additional fully differential input channel. 23 dgnd digital ground. reference point for digital circuitry. 24 v dd digital supply voltage (+2.7v to +3.6v) 25 int interrupt output. a logic low indicates that a new output word is available from the data register. int returns high upon completion of a full output word read operation. int also returns high for short periods (determined by the filter and clock control bits) if no data read has taken place. a logic high indicates internal activity, and a read operation should not be attempted under this condition. int can also provide a strobe to indicate valid data at dout (mdout = 1). 26 dout serial data output. dout outputs data from the internal shift register containing information from the communications register, global setup registers, transfer function registers, or data register. dout can also provide the digital bit stream directly from the s - d modulator (mdout = 1). 27 din serial data input. data on din is written to the input shift register and later transferred to the communications register, global setup registers, special function register, or transfer function registers, depending on the register selection bits in the communications register. 28 sclk serial clock input. apply an external serial clock to transfer data to and from the MAX1403. this serial clock can be continuous, with data transmitted in a train of pulses, or intermittently. if cs is used to frame the data transfer, then sclk may idle high or low between conversions and cs determines the desired active clock edge (see selecting clock polarity ). if cs is tied permanently low, sclk must idle high between data transfers.
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 13 _______________detailed description circuit description the MAX1403 is a low-power, multichannel, serial-output, sigma-delta adc designed for applications with a wide dynamic range, such as weigh scales and pressure transducers. the functional block diagram in figure 2 contains a switching network, a modulator, a pga, two buffers, an oscillator, an on-chip digital filter, two matched transducer excitation current sources, and a bidirectional serial communications port. three fully differential input channels feed into the switching network. each channel may be independent- ly programmed with a gain between +1v/v and +128v/v. these three differential channels may also be configured to operate as five pseudo-differential input channels. two additional, fully differential system-cali- bration channels allow system gain and offset error to be measured. these system-calibration channels can be used as additional differential signal channels when dedicated gain and offset error correction channels are not required. two chopper-stabilized buffers are available to isolate the selected inputs from the capacitive loading of the pga and modulator. three independent dacs provide compensation for the dc component of the input signal on each of the differential input channels. the sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. the pulse train is then processed by a digital decimation filter, resulting in a conversion accuracy exceeding 16 bits. the digital filter? decimation factor is user-selectable, which allows the conversion result? resolution to be reduced to achieve a higher output data rate. when used with 2.4576mhz or 1.024mhz master clocks, the decimation filter can be programmed to produce zeros in its frequency response at the line frequency and associated harmonics. this ensures excellent line rejection without the need for fur- ther postfiltering. in addition, the modulator sampling frequency can be optimized for either lowest power dis- sipation or highest output data rate. agnd v+ dgnd v dd caloff+ out2 out1 calgain+ caloff- calgain- ain1 ain2 ain3 ain4 ain5 ain6 switching network modulator dac pga v+ buffer buffer agnd v+ digital filter sclk din dout int cs ds0 ds1 reset clkin clkout refin+ refin- divider MAX1403 interface and control clock gen figure 2. functional diagram
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 14 ______________________________________________________________________________________ the MAX1403 can be configured to sequentially scan all signal inputs and to transmit the results through the serial interface with minimum communications over- head. the output word contains a channel identification tag to indicate the source of each conversion result. serial digital interface the serial digital interface provides access to eight on- chip registers (figure 3). all serial-interface commands begin with a write to the communications register (comm). on power-up, system reset, or interface reset, the part expects a write to its communications register. the comm register access begins with a 0 start bit. the comm register r/ w bit selects a read or write operation, and the register select bits (rs2, rs1, rs0) select the register to be addressed. hold din high when not writing to comm or another register (table 1). the serial interface consists of five signals: cs , sclk, din, dout, and int . clock pulses on sclk shift bits into din and out of dout. int provides an indication that data is available. cs is a device chip-select input as well as a clock polarity select input (figure 4). using cs allows the sclk, din, and dout signals to be shared among several spi-compatible devices. when short on i/o pins, connect cs low and operate the serial digital interface in cpol = 1, cpha = 1 mode using sclk, din, and dout. this 3-wire interface mode is ideal for opto-isolated applications. furthermore, a microcontroller (such as a pic16c54 or 80c51) can use a single bidirectional i/o pin for both sending to din and receiving from dout (see applications information ), because the MAX1403 drives dout only during a read cycle. additionally, connecting the int signal to a hardware interrupt allows faster throughput and reliable, collision- free data flow. the MAX1403 features a mode where the raw modula- tor data output is accessible. in this mode, the dout and int functions are reassigned (see the modulator data output section). data register d1?0/cid rs0 global setup register 1 global setup register 2 special function register xfer function register 1 xfer function register 2 xfer function register 3 data register d17?10 data register d9?2 communications register rs1 rs2 din dout register select decoder figure 3. register summary din (during write)* dout (during read)* ds1, ds0 msb d6 d5 d4 d3 d2 d1 d0 msb d6 d5 d4 d3 d2 d1 d0 cs int t 10 t 6 t 20 t 19 t 8 t 7 t 17 t 16 t 3 t 1 t 13 t 5 t 4 t 12 t 18 t 9 t 11 t 15 t 14 sclk (cpol = 1) sclk (cpol = 0) *dout is high impedance during the write cycle; din is ignored during the read cycle. figure 4. serial-interface timing table 1. control-register addressing 0 rs1 0 rs0 0 1 global setup register 1 0 1 0 1 1 special function register 0 global setup register 2 communications register 0 0 0 0 0 1 transfer function register 2 1 1 0 1 1 data register 1 transfer function register 3 transfer function register 1 1 1 rs2 target register
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 15 selecting clock polarity the serial interface can be operated with the clock idling either high or low. this is compatible with motorola? spi interface operated in cpol = 1, cpha = 1 mode or cpol = 0, cpha = 1 mode. the clock polarity is deter- mined by the state of sclk at the falling edge of cs . ensure that the setup times t 4 /t 12 and t 5 /t 13 are not violat- ed. if cs is connected to ground, resulting in no falling edge on cs , sclk must idle high (cpol = 1, cpha = 1). data-ready signal (drdy bit true or i i n n t t = low) the data-ready signal indicates that new data may be read from the 24-bit data register. after the end of a suc- cessful data register read, the data-ready signal becomes false. if a new measurement completes before the data is read, the data-ready signal becomes false. the data-ready signal becomes true again when new data is available in the data register. the MAX1403 provides two methods of monitoring the data-ready signal. int provides a hardware solution (active low when data is ready to be accessed), while the drdy bit in the comm register provides a software solution (active high). read data as soon as possible once data-ready becomes true. this becomes increasingly important for faster measurement rates. if the data read is delayed significantly, a collision may result. a collision occurs when a new measurement completes during a data- register read operation. after a collision, information in the data register is invalid. the failed read operation must be completed even though the data is invalid. resetting the interface reset the serial interface by clocking in 32 1s. resetting the interface does not affect the internal reg- isters. if continuous data output mode is in use, clock in eight 0s followed by 32 1s. more than 32 1s may be clocked in, since a leading 0 is used as the start bit for all oper- ations. continuous data output mode when scanning the input channels (scan = 1), the ser- ial interface allows the data register to be read repeat- edly without requiring a write to the comm register. the initial comm write (01111000) is followed by 24 clocks (din = high) to read the 24-bit data register. once the data register has been read, it can be read again after the next conversion by writing another 24 clocks (din = high). terminate the continuous data out- put mode by writing to the comm register with any valid access. modulator data output (mdout = 1) single-bit, raw modulator data is available at dout for custom filtering when mdout = 1. int provides a mod- ulator clock for data synchronization. data is valid on the falling edge of int . write operations can still be performed; however, read operations are disabled. after mdout is returned to 0, valid data is accessed by the normal serial-interface read operation. on-chip registers communications register 0/drdy: (default = 0) data ready bit. on a write, this bit must be reset to 0 to signal the start of the com- munications register data word. on a read, a 1 in this location (0/drdy) signifies that valid data is available in the data register. this bit is reset after the data register is read or, if data is not read, 0/drdy will go low at the end of the next measurement. rs2, rs1, rs0: (default = 0, 0, 0) register select bits. these bits select the register to be accessed (table 1). r/ w : (default = 0) read/write bit. when set high, the selected register is read; when r/ w = 0, the selected register is written. reset: (default = 0) software reset bit. setting this bit high causes the part to be reset to its default power- up condition (reset = 0). stdby: (default = 0) standby power-down bit. setting the stdby bit places the part in ?tandby?condition, shutting down everything except the serial interface and the clk oscillator. fsync: (default = 0) filter sync bit. when fsync = 0, conversions are automatically performed at a data rate determined by clk, fs1, fs0, mf1, and mf0 bits. when fsync = 1, the digital filter and analog modulator first bit (msb) (lsb) function 0 stdby 0 reset 0 name fsync 0 register select bits rs0 0 rs1 0 data rdy defaults rs2 0 0 r/ w 0/drdy communications register
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 16 ______________________________________________________________________________________ are held in reset, inhibiting normal self-timed operation. this bit may be used to convert on command to mini- mize the settling time to valid output data, or to synchro- nize operation of a number of MAX1403s. fsync does not reset the serial interface or the 0/drdy flag. to clear the 0/drdy flag while fsync is active, simply read the data register. global setup register 1 a1, a0: (default = 0, 0) channel-selection control bits. these bits (combined with the state of the diff, m1, and m0 bits) determine the channel selected for con- version according to tables 8, 9, and 10. these bits are ignored if the scan bit is set. mf1, mf0: (default = 0, 0) modulator frequency bits. mf1 and mf0 determine the ratio of clkin oscillator fre- quency to modulator operating frequency. they affect the output data rate, the position of the digital filter notch frequencies, and the power dissipation of the device. achieve lowest power dissipation with mf1 = 0 and mf0 = 0. highest power dissipation and fastest output data rate occur with these bits set to 1, 1 (table 2). clk: (default = 1) clk bit. the clk bit is used in con- junction with x2clk to tell the MAX1403 the frequency of the clkin input signal. if clk = 0, a clkin input fre- quency of 1.024mhz (2.048mhz for x2clk = 1) is expected. if clk = 1, a clkin input frequency of 2.4576mhz (4.9152mhz for x2clk = 1) is expected. this bit affects the decimation factor in the digital filter and thus the output data rate (table 2). fs1, fs0: (default = 0, 1) filter selection bits. these bits (in conjunction with the clk bit) control the deci- mation ratio of the digital filter. they determine the out- put data rate, the position of the digital filter frequency response notches, and the noise present in the output result (table 2). fast: (default 0) fast bit. fast = 0 causes the digital filter to perform a sinc 3 filter function on the modulator data stream. the output data rate will be deter- mined by the values in the clk, fs1, fs0, mf1, and mf0 bits (table 2). the settling time for sinc 3 function is 3 [1 / (output data rate)]. in sinc 3 mode, the MAX1403 automatically holds the drdy signal false (after any significant configuration change) until settled data is available. fast = 1 causes the digital filter to perform a sinc 1 filter function on the modulator data stream. the signal-to-noise ratio achieved with this filter function is less than that of the sinc 3 filter; however, sinc 1 settles in a single output sample period rather than a minimum of three output sample periods for sinc 3 . when switching from sinc 1 to sinc 3 mode, the drdy flag will be deasserted and reasserted after the filter has fully settled. this mode change requires a minimum of three samples. global setup register 2 scan: (default = 0) scan bit. setting this bit to a 1 causes sequential scanning of the input channels as determined by diff, m1, and m0 (see scanning (scan- mode) section). when scan = 0, the MAX1403 repeat- edly measures the unique channel selected by a1, a0, diff, m1, and m0 (table 4). m1, m0: (default 0, 0) mode control bits. these bits control access to the calibration channels caloff and calgain. when scan = 0, setting m1 = 0 and m0 = 1 selects the caloff input, and m1 = 1 and m0 = 0 selects the calgain input (table 3). when scan = 1 and m1 m0, the scanning sequence includes both caloff and calgain inputs (table 4). when scan is set to 1 and the device is scanning the available input channels, selection of either calibration mode (01 or 10) will cause the scanning sequence to be extended to include a conversion on both the calgain+/calgain- input pair and the caloff+/caloff-input pair. the first bit (msb) (lsb) first bit (msb) (lsb) a1 clk 0 1 a0 defaults channel selection 0 mf1 0 mf0 modulator frequency 0 fast name 0 fs1 0 fs0 filter selection 1 function scan diff 0 0 m1 defaults 0 m0 0 buff mode control 0 x2clk name 0 bout 0 iout 0 function global setup register 2 global setup register 1
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 17 exact sequence depends on the state of the diff bit (table 4). when scanning, the calibration channels use the pga gain, format, and dac settings defined by the contents of transfer function register 3. buff: (default = 0) the buff bit controls operation of the input buffer amplifiers. when this bit is 0, the inter- nal buffers are bypassed and powered down. when this bit is set high, the buffers drive the input sampling capacitors and minimize the dynamic input load. diff: (default = 0) differential/pseudo-differential bit. when diff = 0, the part is in pseudo-differential mode, and ain1?in5 are measured respective to ain6, the analog common. when diff = 1, the part is in differen- tial mode with the analog inputs defined as ain1/ain2, ain3/ain4, and ain5/ain6. the available input chan- nels for each mode are tabulated in table 5. note that diff also affects the scanning sequence when the part is placed in scan mode (table 4). bout: (default = 0) burn-out current bit. setting bout = 1 connects 100na current sources to the selected ana- log input channel. this mode is used to check that a transducer has not burned out or opened circuit. the burn-out current source must be turned off (bout = 0) before measurement to ensure best linearity. iout: (default = 0) the iout bit controls the transducer excitation currents. a 0 in this bit disables out1 and out2, effectively making these pins high- impedance. a 1 in this location activates both iout1 and iout2, causing each pin to source 200?. x2clk: (default = 0) times-two clock bit. setting this bit to 1 selects a divide-by-2 prescaler in the clock sig- nal path. this allows use of a higher frequency crystal or clock source and improves immunity to asymmetric clock sources. table 2. data output rate vs. clk, filter select, and modulator frequency bits * data rates offering noise-free 16-bit resolution. note: when fast = 0, f -3db = 0.262 data rate. when fast = 1, f -3db = 0.443 data rate. note: default condition is in bold print. table 3. special modes controlled by m1, m0 (scan = 0) description m1 0 1 normal mode: the device operates normally. calibrate gain: in this mode, the MAX1403 converts the voltage applied across calgain+ and calgain-. the pga gain, dac, and format settings of the selected channel (defined by diff, a1, a0) are used. 1 reserved: do not use. 1 0 0 calibrate offset: in this mode, the MAX1403 converts the voltage applied across caloff+ and caloff-. the pga gain, dac, and format settings of the selected channel (defined by diff, a1, a0) are used. 1 m0 0 2400 4800 400 480 1 1 4.9152 1 2.4576 1200 2400 200 240 1 1 4.9152 0 2.4576 600 1200 100 120 0 1 4.9152 1 2.4576 300 600 50 60 0 1 4.9152 0 2.4576 800 1600 160 200 1 0 2.048 1 1.024 400 800 80 100 1 0 2.048 0 1.024 200 400 40 50 0 0 2.048 1 1.024 100 x2clk = 0 200 20 25 0 0 x2clk = 1 2.048 0 clkin frequency, f clkin (mhz) 1.024 fs1, fs0* (0, 0) fs1, fs0* (0, 1) fs1, fs0 (1, 0) fs1, fs0 (1, 1) available output data rates (sps) clk mf1 mf0
pga MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 18 ______________________________________________________________________________________ special function register (write-only) mdout: (default = 0) modulator out bit. mdout = 0 enables data readout on the dout pin, the normal con- dition for the serial interface. mdout = 1 changes the function of the dout and int pins, providing raw, sin- gle-bit modulator output instead of the normal serial- data interface output. this allows custom filtering directly on the modulator output, without going through the on-chip digital filter. the int pin provides a clock to indicate when the modulator data at dout should be sampled (falling edge of int ). note that in this mode, the on-chip digital filter continues to operate normally. when mdout is returned to 0, valid data may be accessed through the normal serial-interface read operation. fullpd: (default = 0) complete power-down bit. fullpd = 1 forces the part into a complete power-down condition, which includes the clock oscillator. the serial interface continues to operate. the part requires a hard- ware reset to recover correctly from this condition. note: changing the reserved bits in the special-func- tion register from the default status of all 0s will select one of the reserved modes and the part will not operate as expected. this register is a write-only register. however, in the event that this register is mistakenly read, clock 24 bits of data out of the part to restore it to the normal interface-idle state. transfer-function registers the three transfer-function registers control the method used to map the input voltage to the output codes. all of the registers have the same format. the mapping of control registers to associated channels depends on the mode of operation and is affected by the state of m1, m0, diff, and scan (tables 8, 9, and 10). table 4. scan mode scanning sequences (scan = 1) table 5. available input channels (scan = 0) note: all other combinations reserved. special function register (write-only) transfer-function register g2 d3 0 0 defaults g1 pga gain control d0 name offset correction 0 d2 0 0 d1 g0 0 0 u/ b 0 function 0 m1 0 m0 0 1 ain1?in6, ain2?in6, ain3?in6, ain4?in6, ain5?in6, caloff, calgain 0 1 0 0 0 ain1?in2, ain3?in4, ain5?in6 1 ain1?in6, ain2?in6, ain3?in6, ain4?in6, ain5?in6, caloff, calgain ain1?in6, ain2?in6, ain3?in6, ain4?in6, ain5?in6 0 0 0 1 1 0 ain1?in2, ain3ain4, ain5ain6, caloff, calgain 1 ain1?in2, ain3ain4, ain5ain6, caloff, calgain 1 diff sequence first bit (msb) (lsb) 0 0 0 0 0 defaults reserved bits 0 mdout 0 0 0 fullpd name 0 0 0 0 reserved bits 0 function first bit (msb) (lsb) 0 m1 0 m0 0 1 caloff 0 1 0 0 0 ain1?in2, ain3ain4, ain5ain6 1 calgain ain1?in6, ain2?in6, ain3?in6, ain4?in6 0 0 0 1 1 0 calgain 1 caloff 1 diff available channels
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 19 analog inputs ain1 to ain6 inputs ain1 and ain2 map to transfer-function register 1, regardless of scanning mode (scan = 1) or single- ended vs. differential (diff) modes. likewise, ain3 and ain4 inputs always map to transfer-function register 2. finally, ain5 always maps to transfer-function register 3 (input ain6 is analog common). calgain and caloff when not in scan mode (scan = 0), a1 and a0 select which transfer function applies to calgain and caloff. in scan mode (scan = 1), calgain and caloff are always mapped to transfer-function regis- ter 3. note that when scanning while m1 m0, the scan sequence includes both calgain and caloff chan- nels (table 4). caloff always precedes calgain, even though both channels share the same channel id tag (table 11). note that changing the status of any active channel control bits will cause int to immediately transition high and the modulator/filter to be reset. int will reassert after the appropriate digital-filter settling time. the con- trol settings of the inactive channels may be changed freely without affecting the status of int or causing the filter/modulator to be reset. pga gain bits g2?0 control the pga gain according to table 6. unipolar/bipolar mode the u/ b bit places the channel in either bipolar or unipolar mode. a 0 selects bipolar mode, and a 1 selects unipolar mode. this bit does not affect the ana- log-signal conditioning. the modulator always accepts bipolar inputs and produces a bitstream with 50% ones-density when the selected inputs are at the same potential. this bit controls the processing of the digital- filter output, such that the available output bits are mapped to the correct output range. note that u/ b must be set before a conversion is performed; it will not affect any data already held in the output register. selecting bipolar mode does not imply that any input may be taken below agnd. it simply changes the gain and offset of the part. all inputs must remain within their specified operating voltage range. offset-correction dacs bits d3?0 control the offset-correction dac. the dac range depends on the pga gain setting and is expressed as a percentage of the available full-scale input range (table 7). d3 is a sign bit, and d2?0 represent the dac magni- tude. note that when a dac value of 0000 is pro- grammed (the default), the dac is disconnected from the modulator inputs. this prevents the dac from degrading noise performance when offset correction is not required. transfer-function register mapping tables 8, 9, and 10 show the channel-control register mapping in the various operating modes. table 6. pga gain codes table 7. dac code vs. dac value 0 g1 0 g0 0 1 x2 0 1 0 1 1 x8 0 x4 x1 0 0 0 0 0 1 x32 1 1 0 1 1 x128 1 x64 x16 1 1 g2 pga gain -66.7 -100 -116.7 -83.3 +66.7 +100 +116.7 unipolar dac value (% of fsr) +83.3 dac not connected -33.3 -50 -16.7 dac not connected +33.3 +50 +16.7 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 d0 0 1 1 -33.3 -50 1 -58.3 1 1 1 1 1 -41.6 0 1 0 1 0 0 +33.3 +50 0 +58.3 1 1 1 1 0 +41.6 0 1 0 1 bipolar dac value (% of fsr) d3 1 1 -16.7 1 -25 1 0 1 0 1 -8.3 0 0 0 0 0 0 +16.7 0 +25 1 0 1 0 0 +8.3 0 0 d1 0 d2 0
do not use MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 20 ______________________________________________________________________________________ table 8. transfer-function register mapping?ormal mode (m1 = 0, m0 = 0) table 9. transfer-function register mapping?ffset-calibration mode (m1 = 0, m0 = 1) 3 2 3 1 1 3 transfer- function register 2 1 2 2 1 1 2 2 1 ain5?in6 ain3?in4 ain5?in6 ain1?in2 ain1?in2 ain5?in6 channel ain3?in4 ain1?in6 ain3?in6 ain4?in6 ain2?in6 ain1?in6 ain3?in6 ain4?in6 ain2?in6 x x x x 0 1 0 x x x x 1 0 1 a0 0 1 1 1 x 1 x 1 1 x 1 x 0 0 0 1 1 0 scan 0 1 0 1 1 1 1 x 0 x 0 1 x 0 x 0 0 0 0 1 0 1 0 0 0 0 a1 0 diff 0 do not use 1 1 1 1 ain1?in6 x 1 1 x 0 ain3?in4 caloff+?aloff- calgain+?algain- ain5?in6 x x x x 1 1 2 3 1 3 x 1 x 1 1 3 x 1 x 1 ain5?in6 calgain+?algain- ain1?in2 caloff+?aloff- caloff+?aloff- caloff+?aloff- channel caloff+?aloff- do not use ain3?in6 ain4?in6 ain2?in6 caloff+?aloff- caloff+?aloff- caloff+?aloff- caloff+?aloff- x x x x 0 1 0 x x x 1 1 0 1 a0 0 1 1 3 3 1 1 x 1 x 0 1 3 x 0 x 0 0 0 1 3 transfer- function register 1 1 0 scan 2 0 1 0 1 0 1 2 1 2 x 0 x 0 1 1 x 0 1 1 0 0 1 2 0 2 1 0 1 0 0 1 0 0 a1 0 diff 0 do not use 1 1 1 1 do not use 1 0 1 1 x = don? care
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 21 data register (read-only) the data register is a 24-bit, read-only register. any attempt to write data to this location will have no effect. if a write operation is attempted, 8 bits of data must be clocked into the part before it will return to its normal idle mode, expecting a write to the communications register. data is output msb first, followed by one reserved 0 bit, two auxiliary data bits, and a 3-bit channel id tag indi- cating the channel from which the data originated. d17?0: the conversion result. d17 is the msb. the result is in offset binary format. 00 0000 0000 0000 0000 represents the minimum value, and 11 1111 1111 1111 1111 represents the maximum value. inputs exceeding the available input range are limited to the corresponding minimum or maximum output values. 0: this reserved bit will always be 0. first bit (data msb) data register (read-only) bits d17 d13 d16 d15 d14 d10 data bits d12 d11 d9 d5 d8 d7 d6 d2 data bits d4 d3 auxiliary data channel id tag d1 ds0 d0 ? ds1 cid0 data bits cid2 cid1 reserved (data lsb) (lsb) table 10. transfer-function register mapping?ain-calibration mode (m1 = 1, m0 = 0) 0 diff 0 a1 0 0 1 0 0 1 0 1 2 0 2 1 0 0 1 1 0 x 1 1 0 x 0 x 2 1 2 1 0 1 0 1 0 2 scan 0 1 1 transfer- function register 1 x 1 x 3 1 0 0 0 x 0 x 3 1 0 x 1 x 1 1 3 3 1 1 0 a0 1 0 1 1 x x x 0 1 0 3 x x x x calgain+?algain- calgain+?algain- calgain+?algain- calgain+?algain- ain2?in6 ain4?in6 ain3?in6 calgain+?algain- channel 1 calgain+?algain- calgain+?algain- caloff+?aloff- ain1?in2 calgain+?algain- ain5?in6 1 x 1 x 3 1 3 2 1 1 x x x x ain5?in6 calgain+?algain- caloff+?aloff- ain3?in4 0 x 1 1 x ain1?in6 1 1 1 1 do not use do not use x = don? care
ds1, ds0: the status of the auxiliary data input pins. these are latched on the first falling edge of the sclk signal for the current data register read access. cid2?: channel id tag (table 11). switching network a switching network provides selection between three fully differential input channels or five pseudo-differen- tial channels, using ain6 as a shared common. the switching network provides two additional fully differen- tial input channels intended for system calibration, which may be used as extra fully differential signal channels. table 12 shows the channel configurations available for both operating modes. scanning (scan-mode) to sample and convert the available input channels sequentially, set the scan control bit in the global setup register. the sequence is determined by diff (fully differential or pseudo-differential) and by the mode control bits m1 and m0 (tables 8, 9, 10). with scan set, the device automatically sequences through each available channel, transmitting a single conver- sion result before proceeding to the next channel. the MAX1403 automatically allows sufficient time for each conversion to fully settle, to ensure optimum resolution before asserting the data-ready signal and moving to the next available channel. the scan rate is, therefore, dependent on the clock bit (clk), the filter control bits (fs1, fs0), and the modulator frequency selection bits (mf1, mf0). burn-out currents the input circuitry also provides two ?urn-out?cur- rents. these small currents may be used to test the integrity of the selected transducer. they can be selec- tively enabled or disabled by the bout bit in the global setup register. table 12. input channel configuration in fully differential and pseudo-differential mode (scan = 0) x = don? care * this combination is available only in pseudo-differential mode when using the internal scanning logic. ** these combinations are only available in the calibration modes. 0 m0 0 diff 0 0 ain2 0 0 0 0 0 ain4 0 ain3 ain1 0 0 0 1 0 1 ain3 0 0 1 1 x caloff+** 0 ain5 ain1 0 0 0 x 1 x caloff+** m1 0 0 x high input calgain+** ain5* 1 0 0 x calgain+** 1 0 a1 0 1 1 0 0 1 x x x x x mode pseudo- differential fully differential 0 a0 1 0 1 0 1 0 x x x x x ain6 ain6 ain6 ain6 ain4 caloff-** ain6 ain2 caloff-** low input calgain-** ain6* calgain-** calibration ain5?in6 ain3?in4 ain1?in2 ain4?in6 ain3?in6 ain2?in6 ain1?in6 channel cid0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 cid1 cid2 0 0 0 0 1 1 1 1 MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 22 ______________________________________________________________________________________ table 11. channel id tag codes
transducer excitation currents the MAX1403 provides two matched 200? transducer excitation currents at out1 and out2. these currents have low absolute temperature coefficients and tight tc matching. these characteristics enable accurate compensation of errors due to ir drops in long trans- ducer cable runs. they may be enabled or disabled using a single register control bit (iout). dynamic input impedance at the channel selection network when used in unbuffered mode (buff = 0), the analog inputs present a dynamic load to the driving circuitry. the size of the sampling capacitor and the input sam- pling frequency (figure 5) determine the dynamic load seen by the driving circuitry. the MAX1403 samples at a constant rate for all gain settings. this provides a maxi- mum time for the input to settle at a given data rate. the dynamic load presented by the inputs varies with the gain setting. for gains of +2v/v, +4v/v, and +8v/v, the input sampling capacitor increases with the chosen gain. gains of +16v/v, +32v/v, +64v/v, and +128v/v present the same input load as the x8 gain setting. when designing with the MAX1403, as with any other switched-capacitor adc input, consider the advantages and disadvantages of series input resistance. a series resistor reduces the transient-current impulse to the external driving amplifier. this improves the amplifier phase margin and reduces the possibility of ringing. the resistor spreads the transient-load current from the sampler over time due to the rc time constant of the circuit. however, an improperly chosen series resis- tance can hinder performance in fast 16-bit converters. the settling time of the rc network can limit the speed at which the converter can operate properly, or reduce the settling accuracy of the sampler. in practice, this means ensuring that the rc time constant?esulting from the product of the driving source impedance and the capacitance presented by both the MAX1403? input and any external capacitances?s sufficiently small to allow settling to the desired accuracy. tables 13a?3d summarize the maximum allowable series resistance vs. external capacitance for each MAX1403 gain setting in order to ensure 16-bit performance in unbuffered mode. MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 23 r ext c ext r mux c pin r sw c st c sample c c figure 5. analog input, unbuffered mode (buff = 0) table 13a. r ext , c ext values for less than 16-bit gain error in unbuffered (buff = 0) mode?x modulator sampling frequency (mf1, mf0 = 00); x2clk = 0; clkin = 2.4576mhz table 13b. r ext , c ext values for less than 16-bit gain error in unbuffered (buff = 0) mode?x modulator sampling frequency (mf1, mf0 = 01); x2clk = 0; clkin = 2.4576mhz 34 15 34 15 9.8 2 25 13 17 10 7.3 8, 16, 32, 64, 128 8.7 9.8 4 1 c ext = 0pf c ext = 50pf c ext = 100pf 2.9 1.6 2.9 1.6 0.43 2.7 1.5 2.4 1.4 0.37 0.40 pga gain 0.43 c ext = 500pf c ext = 1000pf c ext = 5000pf external resistance, r ext (k ) 17 7.5 17 7.5 4.9 2 13 6.4 8.4 5.0 3.7 8, 16, 32, 64, 128 4.4 4.9 4 1 c ext = 0pf c ext = 50pf c ext = 100pf 1.4 0.81 1.4 0.81 0.22 1.3 0.76 1.2 0.70 0.18 0.20 pga gain 0.22 c ext = 500pf c ext = 1000pf c ext = 5000pf external resistance, r ext (k )
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 24 ______________________________________________________________________________________ table 13c. r ext , c ext values for less than 16-bit gain error in unbuffered (buff = 0) mode?x modulator sampling frequency (mf1, mf0 = 10 ); x2clk = 0; clkin = 2.4576mhz table 13d. r ext , c ext values for less than 16-bit gain error in unbuffered (buff = 0) mode?x modulator sampling frequency (mf1, mf0 = 11); x2clk = 0; clkin = 2.4576mhz r ext c ext r mux c pin r in c st c amp c sample c c figure 6 . analog input, buffered mode (buff = 1) 8.3 3.7 8.3 3.7 2.4 2 6.2 3.2 4.1 2.5 1.8 8, 16, 32, 64, 128 2.2 2.4 4 1 c ext = 0pf c ext = 50pf c ext = 100pf 0.72 0.40 0.72 0.40 0.11 0.67 0.38 0.60 0.35 0.09 0.10 pga gain 0.11 c ext = 500pf c ext = 1000pf c ext = 5000pf external resistance, r ext (k ) 4.1 1.8 4.1 1.8 1.2 2 3.0 1.5 2.0 1.2 0.88 8, 16, 32, 64, 128 1.1 1.2 4 1 c ext = 0pf c ext = 50pf c ext = 100pf 0.35 0.20 0.35 0.20 0.05 0.32 0.18 0.29 0.17 0.04 0.05 pga gain 0.05 c ext = 500pf c ext = 1000pf c ext = 5000pf external resistance, r ext (k ) input buffers the MAX1403 provides a pair of input buffers to isolate the inputs from the capacitive load presented by the pga/modulator (figure 6). the buffers are chopper sta- bilized to reduce the effect of their dc offsets and low- frequency noise. since the buffers can represent more than 50% of the total analog power dissipation, they may be shut down in applications where minimum power dis- sipation is required and the capacitive input load is not a concern. disable the buffers in applications where the inputs must operate close to agnd or v+. when used in buffered mode, the buffers isolate the inputs from the sampling capacitors. the sampling- related gain error is dramatically reduced in this mode. a small dynamic load remains from the chopper stabi- lization. the multiplexer exhibits a small input leakage current of up to 10na. with high source resistances, this leakage current may result in a dc offset.
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 25 table 14. r ext , c ext values for less than 16-bit gain error in buffered (buff = 1) mode?ll modulator sampling frequencies (mf1, mf0 = xx); x2clk = 0; clkin = 2.4576mhz 10 10 10 10 10 2 10 10 10 10 4 1 c ext = 0pf c ext = 50pf c ext = 100pf 10 10 10 10 10 10 10 10 pga gain 10 c ext = 500pf c ext = 1000pf c ext = 5000pf external resistance, r ext (k ) 10 10 10 10 10 16 10 10 10 10 32 8 10 10 10 10 10 10 10 10 10 10 10 10 64 10 10 10 128 10 10 10 10 10 10 reference input the MAX1403 is optimized for ratiometric measure- ments and includes a fully differential reference input. apply the reference voltage across refin+ and refin-, ensuring that refin+ is more positive than refin-. refin+ and refin- must be between agnd and v+. the MAX1403 is specified with a +1.25v reference. modulator the MAX1403 performs analog-to-digital conversion using a single-bit, second-order, switched-capacitor modulator. a single comparator within the modulator quantizes the input signal at a much higher sample rate than the bandwidth of the signal to be converted. the quantizer then presents a stream of 1s and 0s to the digital filter for processing, to remove the frequency- shaped quantization noise. the MAX1403 modulator provides 2nd-order frequency shaping of the quantization noise resulting from the sin- gle bit quantizer. the modulator is fully differential for maximum signal-to-noise ratio and minimum suscepti- bility to power-supply noise. the modulator operates at one of a total of eight differ- ent sampling rates (f m ) determined by the master clock frequency (f clkin ), the x2clk bit, the clk bit, and the modulator frequency control bits mf1 and mf0. power dissipation is optimized for each of these modes by controlling the bias level of the modulator. table 15 shows the input and reference sample rates. pga a programmable gain amplifier (pga) with a user- selectable gain of x1, x2, x4, x8, x16, x32, x64, or x128 (table 6) precedes the modulator. figure 8 shows the default bipolar transfer function with the following illus- trated codes: 1) pga = 0, dac = 0; 2) pga = 3, dac = 0; or 3) pga = 3, dac = 3. output noise tables 16a and 16b show the rms noise for typical out- put frequencies (notches) and -3db frequencies for the MAX1403 with f clkin = 2.4576mhz. the numbers given are for the bipolar input ranges with v ref = +1.25v, with no buffer (buff = 0), and with the buffer inserted (buff = 1). these numbers are typical and are generated at a differential analog input voltage of 0. figure 7 shows graphs of effective resolution vs. gain and notch frequency. the effective resolution values were derived from the following equation: effective resolution = (snr db - 1.76db) / 6.02 the maximum possible signal divided by the noise of the device, snr db , is defined as the ratio of the input full-scale voltage (i.e., 2 v refin / gain) to the output rms noise. note that it is not calculated using peak-to- peak output noise numbers. peak-to-peak noise num- bers can be up to 6.6 times the rms numbers, while effective resolution numbers based on peak-to-peak noise can be 2.5 bits below the effective resolution based on rms noise, as quoted in the tables. the noise shown in tables 16a and 16b is composed of device noise and quantization noise. the device noise is relatively low, but becomes the limiting noise source for high gain settings. the quantization noise is dependent on the notch frequency and becomes the dominant noise source as the notch frequency is increased.
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 26 ______________________________________________________________________________________ table 15. modulator operating frequency, sampling frequency, and 16-bit data output rates table 16a. noise vs. gain and output data rate?nbuffered mode, v ref = 1.25v, f clkin = 2.4576mhz note: default condition is in bold print. 2.048 2.048 0 0 2.048 0 1.024 2.048 0 4.9152 1 2.4576 1.024 1.024 4.9152 1 clkin frequency, f clkin (mhz) clk 16 8 32 16 40, 50 2.4576 64 1.024 32 128 64 38.4 80, 100 20, 25 19.2 50, 60 76.8 ain/refin sampling frequency, f s (khz) modulator frequency, f m (khz) available output data rates at 16-bit accuracy (sps) 38.4 100, 120 160, 200 4.9152 1 2.4576 4.9152 1 2.4576 153.6 76.8 200, 240 307.2 153.6 400, 480 0 1 0 1 0 0 mf1 1 1 0 1 1 0 0 1 mf0 0 1 x2clk = 0 default x2clk = 1 -3db freq. (hz) typical output noise (? rms ) for various programmable gains 60 15.7 5.91 3.20 1.90 1.25 output data rate (sps) 1.13 1.18 1.15 1.15 fs1:fs0 = 1 300 78.6 80.5 38.6 20.6 10.3 5.73 3.62 2.84 2.67 fs1:fs0 = 2 600 157.2 x1 x2 x4 x8 x16 x32 x64 x128 mf1:mf0 = 0 50 13.1 5.42 3.03 1.70 1.11 1.06 1.05 1.05 1.04 fs1:fs0 = 0 441 236 112 54.8 29.2 14.5 7.61 5.13 fs1:fs0 = 3 mf1:mf0 = 1 100 26.2 5.53 2.96 1.73 1.13 1.06 1.06 1.08 1.05 fs1:fs0 = 0 120 31.4 6.06 3.28 1.90 1.25 1.17 1.11 1.12 1.11 fs1:fs0 = 1 600 157.2 81.5 39.9 19.6 10.2 5.45 3.49 2.72 2.59 fs1:fs0 = 2 1200 314.4 450 232 115 53.4 27.8 14.7 8.00 5.08 fs1:fs0 = 3 mf1:mf0 = 2 200 52.4 5.39 2.92 1.70 1.09 1.06 1.02 1.02 1.03 fs1:fs0 = 0 240 62.9 6.27 3.28 1.89 1.20 1.18 1.14 1.17 1.11 fs1:fs0 = 1 1200 314.4 77.8 40.1 20.1 10.0 5.53 3.56 2.74 bit status 2.59 fs1:fs0 = 2 2400 628.8 431 232 109 54.9 28.2 14.1 8.08 4.99 fs1:fs0 = 3 mf1:mf0 = 3 400 104.8 5.36 3.00 1.82 1.17 1.10 1.06 1.10 1.11 fs1:fs0 = 0 480 125.7 5.88 3.25 1.94 1.28 1.26 1.16 1.17 1.15 fs1:fs0 = 1 2400 628.8 79.7 39.6 20.2 10.5 5.74 3.63 3.02 2.76 fs1:fs0 = 2 4800 1258 441 227 111 55.5 29.7 14.6 7.73 5.43 fs1:fs0 = 3
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 27 10 12 11 14 13 16 15 17 19 18 20 148 2 163264128 gain (v/v) b) buff = 1 a) buff = 0 effective resolution (bits) 10 12 11 14 13 16 15 17 19 18 20 148 2 163264128 256 256 gain (v/v) effective resolution (bits) fs1: fs0 = 0 or 1 fs1: fs0 = 2 fs1: fs0 = 3 clk = 1 fs1: fs0 = 0 or 1 fs1: fs0 = 2 fs1: fs0 = 3 clk = 1 buff = 1 clk = 1 buff = 0 figure 7. effective resolution vs. gain and notch frequency table 16b. noise vs. gain and output data rate?uffered mode, v ref = 1.25v, f clkin = 2.4576mhz -3db freq. (hz) typical output noise (? rms ) for various programmable gains output data rate (sps) x1 x2 x4 x8 x16 x32 x64 x128 mf1:mf0 = 0 50 13.1 5.72 3.21 2.10 1.41 1.42 1.44 1.38 1.34 fs1:fs0 = 0 60 15.7 6.29 3.57 2.30 1.55 1.61 1.56 1.49 1.56 fs1:fs0 = 1 300 78.6 80.6 39.8 19.3 10.2 6.14 4.25 3.03 3.52 fs1:fs0 = 2 600 157.2 436 225 116 57.1 28.8 15.0 8.70 5.99 fs1:fs0 = 3 mf1:mf0 = 1 100 26.2 5.82 3.35 2.08 1.43 1.37 1.36 1.35 1.31 fs1:fs0 = 0 120 31.4 6.01 3.65 2.27 1.51 1.51 1.50 1.50 1.47 fs1:fs0 = 1 600 157.2 77.7 40.1 20.2 10.6 5.93 4.19 3.54 3.23 fs1:fs0 = 2 1200 314.4 434 222 111 57.0 28.3 14.8 8.37 5.81 fs1:fs0 = 3 mf1:mf0 = 2 bit status 200 52.4 5.82 3.07 1.87 1.26 1.20 1.18 1.15 1.17 fs1:fs0 = 0 240 62.9 6.17 3.54 2.09 1.45 1.30 1.27 1.31 1.29 fs1:fs0 = 1 1200 314.4 79.0 41.1 19.8 10.5 5.68 3.68 3.14 2.99 fs1:fs0 = 2 2400 628.8 439 226 111 57.9 28.7 15.4 8.26 5.32 fs1:fs0 = 3 mf1:mf0 = 3 400 104.8 5.60 3.10 1.85 1.32 1.24 1.25 1.19 1.21 fs1:fs0 = 0 480 125.7 6.18 3.47 2.02 1.38 1.37 1.29 1.33 1.33 fs1:fs0 = 1 2400 628.8 76.3 39.3 20.8 9.83 5.92 3.92 3.92 3.07 fs1:fs0 = 2 4800 1258 455 225 114 57.1 29.9 14.5 8.13 5.55 fs1:fs0 = 3
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 28 ______________________________________________________________________________________ offset-correction dac the MAX1403 provides a coarse (3-bit plus sign) offset- correction dac at the modulator input. use this dac to remove the offset component in the input signal, allow- ing the adc to operate on a more sensitive range. the dac offsets up to ?16.7% of the selected range in ?6.7% increments for unipolar mode, and up to ?8.3% of the selected range in ?.3% increments for bipolar mode. when a dac value of 0 is selected, the dac is completely disconnected from the modulator inputs and does not contribute any noise. figures 8 and 9 show the effect of the dac codes on the input range and transfer function. clock oscillator the clock oscillator may be used with an external crystal (or resonator) connected between clkin and clkout, or may be driven directly by an external oscillator at clkin with clkout left unconnected. in normal oper- ating mode, the MAX1403 is specified for operation with clkin at either 1.024mhz (clk = 0) or 2.4576mhz (clk = 1, default). when operated at these frequencies, the device may be programmed to produce frequency response nulls at the local line frequency (either 60hz or 50hz) and the associated line harmonics. in standby mode (stby = 1) all circuitry, with the exception of the serial interface and the clock oscillator, is powered down. the interface consumes minimal power with a static sclk. enter power-down mode (including the oscillator) by setting the fullpd bit in the special-function register. when exiting a full-power shutdown, perform a hardware reset or a software reset after the master clock signal is established (typically 10ms when using the on-board oscillator with an exter- nal crystal) to ensure that any potentially corrupted reg- isters are cleared. it is often helpful to use higher-frequency crystals or resonators, especially for surface-mount applications where the result may be reduced pc board area for the oscillator component and a lower price or better com- ponent availability. also, it may be necessary to oper- ate the part with a clock source whose duty cycle is not close to 50%. in either case, the MAX1403 can operate with a master clock frequency of up to 5mhz, and includes an internal divide-by-2 prescaler to restore the internal clock frequency to a range of up to 2.5mhz with a 50% duty cycle. to activate this prescaler, set the x2clk bit in the control registers. note that using clkin frequencies above 2.5mhz in combination with the x2clk mode will result in a small increase in digital supply current. dac code d3: d2: d1: d0: input voltage range (v ref = 1.25v pga = 000) -7 1 1 1 1 -6 1 1 1 0 -5 1 1 0 1 -4 1 1 0 0 -3 1 0 1 1 -2 1 0 1 0 -1 1 0 1 0 0 0 0 0 0 +1 0 0 0 1 +2 0 0 1 0 +3 0 0 1 1 +4 0 1 0 0 +5 0 1 0 1 +6 0 1 1 0 +7 0 1 1 1 2.708v 2.50v 2.292v 2.083v 1.875v 1.667v 1.458v 1.25v 1.042v 0.833v 0.625v 0.416v 0.208v 0v -0.208v -0.416v -0.625v -0.833v -1.042v -1.25v -1.458v -1.667v -1.875v -2.083v -2.292v -2.50v -2.708v 13/6 v ref /2 pga 2 v ref /2 pga 11/6 v ref /2 pga 10/6 v ref /2 pga 9/6 v ref /2 pga 8/6 v ref /2 pga 7/6 v ref /2 pga v ref /2 pga 5/6 v ref /2 pga 4/6 v ref /2 pga 3/6 v ref /2 pga 2/6 v ref /2 pga 1/6 v ref /2 pga 0 -1/6 v ref /2 pga -2/6 v ref /2 pga -3/6 v ref /2 pga -4/6 v ref /2 pga -5/6 v ref /2 pga -v ref /2 pga -7/6 v ref /2 pga -8/6 v ref /2 pga -9/6 v ref /2 pga -10/6 v ref /2 pga -11/6 v ref /2 pga -2 v ref /2 pga -13/6 v ref /2 pga maximum input minimum input (u/b = 1) minimum input (u/b = 0) figure 9. input voltage range vs. dac code zero-scale 2621 midscale 131072 negative dac step shifts the transfer function toward the positive rail. pga = 3 dac = 0 pga = 0 dac = 0 pga = 3 dac = +3 max code 262144 full-scale 259522 input voltage range code (v ain -)-v ref agnd (v ain -) - v ref /8 - v ref /16 (v ain -) - v ref /8 - v ref /16 (v ain -) - v ref /8 (v ain -) + v ref /8 v+ (v ain -) + v ref (v ain- ) figure 8. effect of pga and dac codes on the bipolar transfer function
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 29 digital filter the on-chip digital filter processes the 1-bit data stream from the modulator using a sinc 3 or sinc 1 fil- ter. the sinc filters are conceptually simple, efficient, and extremely flexible, especially where variable reso- lution and data rates are required. also, the filter notch positions are easily controlled since they are directly related to the output data rate (1 / data word period). the sinc 1 function results in a faster settling response while retaining the same frequency response notches as the default sinc 3 filter. this allows the filter to settle faster at the expense of resolution and quantization noise. the sinc 1 filter settles in one data word period. with 60hz notches (60hz data rate), the settling time would be 1 / 60hz or 16.7ms, whereas the sinc 3 filter would settle in 3 / 60hz or 50ms. toggle between these filter responses using the fast bit in the global setup register. use sinc 1 mode for faster settling and switch to sinc 3 mode when full accuracy is required. switch from the sinc 1 to sinc 3 mode by resetting the fast bit low. the drdy signal will go false and will be reasserted when valid data is available, a minimum of three data- word periods later. the digital filter can be bypassed by setting the mdout bit in the global setup register. when mdout = 1, the raw output of the modulator is directly available at dout. filter characteristics the MAX1403 digital filter implements both a sinc 1 (sinx/x) and sinc 3 (sinx/x) 3 lowpass filter function. the transfer function for the sinc 3 function is that of three cascaded sinc 1 filters described in the z-domain by: and in the frequency domain by: where n, the decimation factor, is the ratio of the modu- lator frequency f m to the output frequency f n . figure 10 shows the filter frequency response. the sinc 3 characteristic cutoff frequency is 0.262 times the first notch frequency. this results in a cutoff frequency of 15.72hz for a first filter notch frequency of 60hz. the response shown in figure 10 is repeated at either side of the digital filter? sample frequency (f m ) and at either side of the related harmonics (2f m , 3f m , . . .). the response of the sinc 3 filter is similar to that of a sinc 1 (averaging filter) filter but with a sharper rolloff. the output data rate for the digital filter corresponds with the positioning of the first notch of the filter? fre- quency response. therefore, for the plot of figure 10 where the first notch of the filter is at 60hz, the output data rate is 60hz. the notches of this (sinx/x) 3 filter are repeated at multiples of the first notch frequency. the sinc 3 filter provides an attenuation of better than 100db at these notches. determine the cutoff frequency of the digital filter by the value loaded into clk, x2clk, mf1, mf0, fs1, and fs0 in the global setup register. programming a different cutoff frequency with fs0 and fs1 does not alter the profile of the filter response; it changes the frequency of the notches. for example, figure 11 shows a cutoff fre- quency of 13.1hz and a first notch frequency of 50hz. for step changes at the input, a settling time must be allowed before valid data can be read. the settling time depends upon the output data rate chosen for the filter. the settling time of the sinc 3 filter to a full-scale step input can be up to four-times the output data period. for a synchronized step input (using the fsync func- tion or the internal scanning logic), the settling time is three-times the output data period. h(f) 1 n sin n f f sin f f m m 3 = ? ? ? ? ? ? ? ? ? ? p p h(z) 1 n 1 z 1 z n 1 3 = - ? ? - - -160 -120 -140 -100 -80 -60 -20 -40 0 0 406080 20 100 120 140 160 180 200 frequency (hz) gain (db) f clkin = 2.4576mhz mf1, 0 = 0 fs1, 0 = 1 f n = 60hz figure 10. frequency response of the sinc 3 filter (notch at 60hz)
analog filtering the digital filter does not provide any rejection close to the harmonics of the modulator sample frequency. however, due to the high oversampling ratio of the MAX1403, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. therefore, the analog filtering requirements in front of the MAX1403 are considerably reduced compared to a conventional converter with no on-chip filtering. in addi- tion, because the part? common-mode rejection of 90db extends out to several khz, common-mode noise susceptibility in this frequency range is substantially reduced. depending on the application, it may be necessary to provide filtering prior to the MAX1403 to eliminate unwanted frequencies the digital filter does not reject. it may also be necessary in some applications to provide additional filtering to ensure that differential noise sig- nals outside the frequency band of interest do not satu- rate the analog modulator. if passive components are placed in front of the MAX1403, when the part is used in unbuffered mode, ensure that the source impedance is low enough not to introduce gain errors in the system (tables 13a?3d). this can significantly limit the amount of passive anti- aliasing filtering that can be applied in front of the MAX1403 in unbuffered mode. however, when the part is used in buffered mode, large source impedances will simply result in a small dc offset error (a 1k source resistance will cause an offset error of less than 10?). therefore, where any significant source impedances are required, maxim recommends operating the part in buffered mode. calibration channels two fully differential calibration channels allow mea- surement of the system gain and offset errors. connect the caloff channel to 0v and the calgain channel to the reference voltage. average several measure- ments on both caloff and calgain. subtract the average offset code and scale to correct for the gain error. this linear calibration technique can be used to remove errors due to source impedances on the analog input (e.g., when using a simple rc anti-aliasing filter on the front end). applications information spi interface (68hc11, pic16c73) microprocessors with a hardware spi (serial peripheral interface) can use a 3-wire interface to the MAX1403 (figure 12). the spi hardware generates groups of eight pulses on sclk, shifting data in on one pin and out on the other pin. for best results, use a hardware interrupt to monitor the int pin and acquire new data as soon as it is available. if hardware interrupts are not available, or if interrupt latency is longer than the selected conversion rate, use the fsync bit to prevent automatic measurement while reading the data output register. the example code in listing 1 shows how to interface with the MAX1403 using a 68hc11. system-dependent initialization code is not shown. MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 30 ______________________________________________________________________________________ v dd ss interrupt sck miso mosi reset int sclk dout din cs v dd 68hc11 MAX1403 figure 12. MAX1403 to 68hc11 interface -160 -140 -100 -120 -80 -60 -20 -40 0 0 406080 20 100 120 140 160 180 200 frequency (hz) gain (db) f clkin = 2.4576mhz mf1, 0 = 0 fs1, 0 = 0 f n = 50hz figure 11. frequency response of the sinc 3 filter (notch at 50hz)
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 31 /* assumptions: ** the max140x's cs pin is tied to ground ** the max140x's int pin drives a falling-edge-triggered interrupt ** max140x's din is driven by mosi, dout drives miso, and sclk drives sclk */ /* low-level function to write 8 bits using 68hc11 spi */ void writebyte (byte x) { /* system-dependent: write to spi hardware and wait until it is finished */ hc11_spdr = x; while (hc11_spsr & hc11_spsr_spif) { /* idle loop */ } } /* low-level function to read 8 bits using 68hc11 spi */ byte readbyte (void) { /* system-dependent: use spi hardware to clock in 8 bits */ hc11_spdr = 0xff; while (hc11_spsr & hc11_spsr_spif) { /* idle loop */ } return hc11_spdr; } /* low-level interrupt handler called whenever the max140x's int pin goes low. ** this function reads new data from the max140x and feeds it into a ** user-defined function process_data(). */ void handledrdy (void) { byte data_h_bits, data_m_bits, data_l_bits; /* storage for data register */ writebyte(0x78); /* read the latest data regsiter value */ data_h_bits = readbyte(); data_m_bits = readbyte(); data_l_bits = readbyte(); process_data(data_h_bits, data_m_bits, data_l_bits); /* system-dependent: re-enable the interrupt service routine */ } /* high-level function to configure the max140x's registers ** refer to data sheet for custom setup values. */ void initialize (void) { /* system-dependent: configure the spi hardware (cpol=1,cpha=1) */ /* write to all of configuration registers */ my_gs1 = 0x0a; my_gs2 = 0x00; my_gs3 = 0x00; my_tf1 = 0x00; my_tf2 = 0x00; my_tf3 = 0x00; writebyte(0x10); writebyte(my_gs1); /* write global setup 1 */ writebyte(0x20); writebyte(my_gs2); /* write global setup 2 */ writebyte(0x30); writebyte(my_gs3); /* write global setup 3 */ writebyte(0x40); writebyte(my_tf1); /* write transfer function 1 */ writebyte(0x50); writebyte(my_tf2); /* write transfer function 2 */ writebyte(0x60); writebyte(my_tf3); /* write transfer function 3 */ /* system-dependent: enable the data-ready (drdy) interrupt handler */ } listing 1. example spi interface
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc 32 ______________________________________________________________________________________ bit-banging interface (80c51, pic16c54) any microcontroller can use general-purpose i/o pins to interface to the MAX1403. if a bidirectional or open- drain i/o pin is available, reduce the interface pin count by connecting din to dout (figure 13). listing 2 shows how to emulate the spi in software. use the same initialization routine shown in listing 1. for best results, use a hardware interrupt to monitor the int pin and acquire new data as soon as it is available. if hardware interrupts are not available, or if interrupt latency is longer than the selected conversion rate, use the fsync bit to prevent automatic measurement while reading the data output register. /* low-level function to write 8 bits ** the example shown here is for a bit-banging system with (cpol=1, cpha=1) */ void writebyte (byte x) { drive sck pin high count = 0; while (cout <= 7) { if (bit 7 of x is 1) drive din pin high else drive din pin low drive sck pin low x = x * 2; drive sck pin high count = count + 1; } } /* low-level function to read 8 bits ** the example shown here is for a bit-banging system with (cpol=1, cpha=1) */ byte readbyte (void) { x = 0; drive sck pin high count = 0; while (cout <= 7) { x = x * 2; drive sck pin low if (dout pin is high) x = x + 1; drive sck pin high count = count + 1; } } return x; listing 2. bit-banging spi replacement v dd p3.0 p3.1 reset dout din sclk cs 8051 MAX1403 figure 13. MAX1403 to 8051 interface
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 33 strain-gauge operation connect the differential inputs of the MAX1403 to the bridge network of the strain gauge. in figure 14, the analog positive supply voltage powers the bridge net- work and the MAX1403 along with its reference voltage. the on-chip pga allows the MAX1403 to handle an analog input voltage range as low as 10mv full scale. the differential inputs of the device allow this analog input range to have an absolute value anywhere between agnd and v+. temperature measurement figure 15 shows a connection from a thermocouple to the MAX1403. in this application, the MAX1403 is oper- ated in its buffered mode to allow large decoupling capacitors on the front end. these decoupling capaci- tors eliminate any noise pickup from the thermocouple leads. when the MAX1403 is operated in buffered mode, it has a reduced common-mode range. in order to place the differential voltage from the thermocouple on a suitable common-mode voltage, the ain2 input of the MAX1403 is biased at the reference voltage, +1.25v. buffer buffer divider clock gen modulator digital filter v+ v+ v dd agnd out1 out2 refin+ refin- agnd dgnd ain1 ain2 switching network active gauge dummy gauge r ref analog supply r r additional analog and calibration channels interface and control sclk din dout int cs reset ds1 ds0 clkin clkout pga dac MAX1403 buffer buffer figure 14. strain-gauge application with MAX1403
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc loop-powered, 4?0ma transmitters low-power, single-supply operation, and easy interfac- ing with optocouplers make the MAX1403 ideal for loop-powered 4?0ma transmitters. loop-powered transmitters draw their power from the 4?0ma loop, limiting the transmitter circuitry to a current budget of 4ma. tolerances in the loop further limit this current budget to 3.5ma. since the MAX1403 consumes only 250?, a total of 3.25ma remains to power the remain- ing transmitter circuitry. figure 16 shows a block dia- gram for a loop-powered 4?0ma transmitter. 3-wire and 4-wire rtd configurations tightly matched 200? current sources compensate for errors in 3-wire and 4-wire rtd configurations. in the 3- wire configuration (figure 17), the lead resistances result in errors if only one current source is used. the 200? will flow through r l1 developing a voltage error between ain1 and ain2. an additional current source compensates for this error by developing an equivalent voltage across r l2 , ensuring the differential voltage at ain1 and ain2 is not affected by lead resistance. this assumes both leads are of the same material and of equal length (r l1 = r l2 ), and assumes out1 and out2 have matching tempcos (5ppm/?). both current sources will flow through r l3 , developing a common- mode voltage that will not affect the differential voltage at ain1 and ain2. using one of the current sources to supply the reference voltage ensures a more accurate ratiometric result. dac r gain r ofst r x v in+ v in- r sense 4?0ma loop interface r fdbk r y c c isolation barrier v+ gnd v+ 4 spi 4 spi 3 spi gnd sensor voltage regulator m p/ m c MAX1403 figure 16. 4?0ma transmitter c c +3v +1.25v refin+ refin- agnd dgnd r r thermocouple junction switching network pga MAX1403 buffer ain1 ain2 figure 15. thermocouple application with MAX1403 34 ______________________________________________________________________________________
MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc ______________________________________________________________________________________ 35 unlike the 3-wire configuration, the 4-wire configuration (figure 18) has no error associated with lead resis- tances, as no current flows in the measurement leads connected to ain1 and ain2. current source out1 provides the excitation current for the rtd, and current source out2 provides current to generate the refer- ence voltage. this reference voltage, developed across r ref , ensures that the analog input voltage span remains ratiometric to the reference voltage. rtd temp- co errors in the analog input voltage are due to the tem- perature drift of the rtd current source and are compensated for by the variation in the reference volt- age. a common resistance value for the rtd is 100 , generating a 20mv signal directly handled at the ana- log input of the MAX1403. the voltage at out1 and out2 can go to within 1.0v of the v+ supply. power supplies no specific power sequence is required for the MAX1403; either the v+ or the vdd supply can come up first. while the latchup performance of the MAX1403 is good, to avoid latchup it is important that power be applied to the MAX1403 before the analog input signals (ain_) or the clkin inputs. if this is not possible, then the current flow into any of these pins should be limited to 50ma. if separate supplies are used for the MAX1403 and the system digital circuitry, then the MAX1403 should be powered up first. grounding and layout for best performance, use printed circuit boards with separate analog and digital ground planes. wire-wrap boards are not recommended. design the printed circuit board so that the analog and digital sections are separated and confined to different areas of the board. join the digital and analog ground planes at only one point. if the MAX1403 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the MAX1403. in systems where mul- tiple devices require agnd to dgnd connections, the connection should still be made at only one point. make the star ground as close to the MAX1403 as possible. avoid running digital lines under the device because these may couple noise onto the die. run the analog ground plane under the MAX1403 to minimize coupling of digital noise. make the power-supply lines to the MAX1403 as wide as possible to provide low-imped- ance paths and reduce the effects of glitches on the power-supply line. figure 18. 4-wire rtd application v+ 200 m a +3v v dd out2 refin+ ain1 ain2 agnd dgnd pga modulator gain = 1 to 128 200 m a rtd r ref refin- out1 MAX1403 dgnd gain = 1 to 128 pga modulator MAX1403 200 m a 200 m a out1 ain1 12.5k ain2 out2 agnd r l3 r l2 r l1 v+ v dd refin- refin+ rtd figure 17. 3-wire rtd application
MAX1403 +5v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. MAX1403 +3v, 18-bit, low-power, multichannel, oversampling (sigma-delta) adc transistor count: 34,648 substrate connected to agnd chip information package information shield fast switching signals, such as clocks, with digi- tal ground to avoid radiating noise to other sections of the board. avoid running clock signals near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough on the board. a microstrip technique is best but is not always possible with double-sided boards. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is important when using high-resolu- tion adcs. decouple all analog supplies with 10? tan- talum capacitors in parallel with 0.1? hf ceramic capacitors to agnd. place these components as close to the device as possible to achieve the best decou- pling. see the MAX1403 evaluation kit manual for the recom- mended layout. the evaluation board package includes a fully assembled and tested evaluation board. ssop.eps

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